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171	676 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 5, MAY 2009 System-Level Power Management Using Online Learning Add to Reading List Source URL: seelab.ucsd.edu Language: English - Date: 2012-06-04 16:50:19 Energy conservation Computers and the environment Power management Central processing unit Computer performance Dynamic voltage scaling Idle Standard Performance Evaluation Corporation
172	yescrypt - a Password Hashing Competition submission Name of the submitted scheme: Name and email address of the submitter(s): Originally submitted on: This revision: Add to Reading List Source URL: password-hashing.net Language: English - Date: 2015-10-25 04:56:20 Computing Computer architecture Cryptography Central processing unit Parallel computing Instruction set architectures Scrypt Salsa20 SIMD ARM architecture X86 SHA-2
173	The Price of Safety: Evaluating IOMMU Performance Muli Ben-Yehuda IBM Haifa Research Lab Jimi Xenidis IBM Research Add to Reading List Source URL: www.mulix.org Language: English - Date: 2016-06-16 09:04:37 Computer hardware Computing Software Memory management Central processing unit Inputoutput memory management unit Computer memory Computer architecture Xen IBM Translation Control Entry Memory-mapped I/O Hypervisor
174	CFIMon: Detecting Violation of Control Flow Integrity using Performance Counters Yubin Xia† ‡, Yutao Liu† ‡, Haibo Chen†, Binyu Zang‡ †Institute of Parallel and Distributed Systems, Shanghai Jiao Tong Unive Add to Reading List Source URL: ipads.se.sjtu.edu.cn Language: English - Date: 2012-08-23 22:16:01 Central processing unit Machine code Software bugs Return-oriented programming Computer memory Instruction set architectures Buffer overflow protection Self-modifying code Subroutine Stack Return-to-libc attack Instruction set
175	HexPADS: a platform to detect “stealth” attacks Mathias Payer Purdue University Abstract. Current systems are under constant attack from many different sources. Both local and remote attackers try to escalate their p Add to Reading List Source URL: hexhive.github.io Language: English - Date: 2016-06-13 11:08:40 Computer memory Computer architecture Central processing unit Cache CPU cache Parallel computing Row hammer Dynamic random-access memory Shared memory Microarchitecture Draft:Cache memory Cold boot attack
176	From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware Haibo Chen† , Xi Wu† , Liwei Yuan† , Binyu Zang† , Pen-chung Yew‡ , and Frederic T. Chong§ † ‡ Add to Reading List Source URL: ipads.se.sjtu.edu.cn Language: English - Date: 2012-01-05 23:25:08 Computer architecture Computing Computer engineering Central processing unit Instruction set architectures Processor register Itanium X86 CPU cache Optimizing compiler 64-bit computing Pointer
177	Computer Performance Microscopy with S HIM Xi Yang‡ Stephen M. Blackburn‡ National University Add to Reading List Source URL: users.cecs.anu.edu.au Language: English - Date: 2015-05-04 22:42:26 Digital signal processing Central processing unit Microprocessors Parallel computing Signal processing Profiling Sampling Instructions per cycle Audio bit depth Multi-core processor Multithreading
178	University of Central Missouri Federal Compliance Requirements Assignment of Credits, Program Length, and Tuition Credits The University of Central Missouri (UCM) awards both undergraduate and graduate credit. The Add to Reading List Source URL: www.ucmo.edu Language: English - Date: 2014-03-08 00:16:46 Education Academia Euthenics Academic transfer Course credit Carnegie Unit and Student Hour Distance education Academic term Course Open University of Sri Lanka FutureSkills High School Massive open online course
179	Accurate emulation of CPU performance Tomasz Buchert1 , Lucas Nussbaum2 , and Jens Gustedt1 1 2 INRIA Nancy – Grand Est Add to Reading List Source URL: www.loria.fr Language: English Computer architecture Computing Computer engineering Clock signal Central processing unit CPU time Multi-core processor Load SpeedStep Clock rate Opteron Benchmark
180	Efficient and scaLable paraVirtual I/o System (ELVIS) Nadav Har’El× Muli Ben-Yehuda×,¤ × IBM Add to Reading List Source URL: www.mulix.org Language: English - Date: 2016-06-16 09:04:09 Computer architecture Central processing unit Hypervisor Paravirtualization Thread Hyper-V Scheduling Scalability Protection ring

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